The present invention relates to a surface mount type semiconductor package and a manufacturing method of this semiconductor package.
A column grid array semiconductor package and a manufacturing method of the same are disclosed in Japanese Patent Laid-Open Publication No. Hei 10-163406.
In a semiconductor package set forth in the above publication, a semiconductor chip having connection terminals is mounted on one surface of a dielectric substrate and the connection terminals of the semiconductor chip are connected through bonding wires to conductive patterns formed on the one surface of the dielectric substrate. The conductive patterns are connected to conductors passing through the dielectric substrate, and the conductors are exposed on the other surface of the dielectric substrate so as to be connectable to a mother board. The semiconductor chip and the conductive patterns are encapsulated by a resin on the dielectric substrate.
According to a method for manufacturing a semiconductor package disclosed in the above-mentioned publication, on the dielectric substrate with a semiconductor chip mounted on it, a conductive layer to form the conductive patterns on one surface of the substrate is formed all over the one surface of the substrate. Holes to form the conductors are formed to pass in the thickness direction in the dielectric substrate. Those through-holes extend to the conductive layer on the dielectric substrate and further pass through the conductive layer and are open to the outside.
After the holes passing through the conductive layer and the dielectric substrate have been formed, the conductive layer has its unnecessary portions removed and is covered with photoresist for use in patterning to form the conductive patterns by the remaining portions of the conductive layer.
By the formation of the photoresist layer, one-end sides of the holes passing through the dielectric substrate and the conductive layer on the substrate are closed by the photoresist layer, and under this condition, a plating process is carried out to fill up the through-holes.
By this plating process, the conductors to fill up the holes are formed, and then the photoresist layer is subjected to patterning by the exposure and development steps, and conductive patterns are formed by selective etching of the conductive layer with the patterned photoresist used as an etching mask.
However, the formation of the conductors is performed before patterning of the photoresist, in other words, before the conductive patterns are formed; therefore, the one-end sides of the holes are closed by the photoresist in the process of forming the conductors, and when a semiconductor structure is dipped in a plating liquid and the liquid enters the open end sides of the holes, there are no leak holes for air bubbles to escape from the holes, so that voids often occur in the conductors due to the bubbles remaining in the holes.
The voids give rise to increased electric resistance or faulty connections at the conductors.
According to the above-mentioned method, the conductors are in contact with the conductive layer only on their circumferential surfaces.
For this reason, sufficient strength cannot be secured at electrical connection of the conductors with the conductive patterns formed by patterning of the conductive layer, leaving a possibility of faulty contact between them.
Therefore, an object of the present invention is to provide a surface mount type semiconductor package, which is free from increased electrical resistance due to voids that occur in the conductors, and a manufacturing method therefore.
Another object of the present invention is to provide a surface mount type semiconductor package that ensures electrical connection of the conductors with the conductive patterns.
To achieve the above objects, the present invention adopts the following configurations.
In an aspect of the present invention, a surface mount type semiconductor package comprises a semiconductor chip having a connection terminal; a dielectric substrate with the semiconductor chip mounted thereon, the dielectric substrate having on one surface with the semiconductor chip mounted thereon a conductive pattern connected to the connection terminal of the semiconductor chip and also having a hole formed passing in the thickness direction through the dielectric substrate; and a conductor located in the through-hole to fill up the through-hole, with one end connected to the conductive pattern and the other end serving as a connection end to a mother board on the other surface of the dielectric substrate, the semiconductor chip and the conductive pattern being encapsulated by a resin on the dielectric substrate, wherein the one end of the conductor is electrically connected to the conductive pattern at a circumferential surface of the conductive pattern defining the through-hole in the conductive pattern and also at an opening edge portion of the through-hole on the conductive pattern.
At one end of the conductor, a wide-diameter portion may be formed covering the opening edge portion of the upper surface of the conductive pattern and therefore the conductor is, at a circumferential surface near the wide-diameter portion of the conductor, in contact with the circumferential surface of the conductive pattern and, at a flat surface of the wide-diameter portion of the conductor, in contact with the opening edge portion.
The conductor may have a small-diameter portion passing through the conductive pattern and also have at the end of the small-diameter portion a wide-diameter portion covering the opening edge portion of the conductive pattern.
Further, the conductor may have a small-diameter portion passing through the conductive pattern and is at a flat surface of a shoulder portion defining the small-diameter portion and at the circumferential surface of the small-diameter portion electrically connected respectively to the circumferential surface of the conductive pattern and the opening edge portion on the lower surface of the conductive pattern.
In another aspect of the present invention, a surface mount type semiconductor package comprises a dielectric substrate having an upper surface and a lower surface; a first hole passing from the upper surface to the lower surface of the substrate; a conductive pattern formed on the upper surface of the substrate; a semiconductor chip mounted on the upper surface of the substrate and electrically connected to the conductive pattern; and a conductor made of a conductive material extending from the upper surface of the substrate through the first hole to the lower surface of the substrate, wherein the conductor is formed onto the conductive pattern and is formed with an external connection terminal at the other end.
When the through-hole is filled with a conductive material to form the conductor, the conductor may be formed by drawing a molten conductive material into the through-hole by a negative pressure. After the through-hole is filled with the conductive material, the conductive material is solidified, by which the conductor is formed.
The conductor may be formed by having a molten conductive material dripped into the through-hole from one end of the through-hole to fill up the through-hole by the conductive material, and the conductive material is solidified and the conductor is formed.
Instead of the example described above, the conductor may be formed by electrolytic plating or electroless plating. Also in this case, one end of the through-hole may be used as a leak hole, so that a conductor without voids can be formed.
Before the conductor is formed, a dielectric layer may be formed which selectively exposes an opening edge portion of the conductive pattern, then the conductor may be formed so as to be monolithic with a wide-diameter portion that fills up a space of the opening edge portion exposed from the dielectric layer. Thus, the conductor, which is securely connected to the conductive pattern, can be formed with relatively easily.
In an additional aspect of the present invention, a surface mount type semiconductor package comprises a dielectric substrate having an upper surface and a lower surface; a first hole passing from the upper surface of the substrate to the lower surface of the substrate; a second hole provided at a location corresponding to the first hole, and the second hole whose circumference is smaller than the that of the first hole; a conductive pattern formed on the upper surface of the substrate; a semiconductor chip mounted on the upper surface of the substrate and electrically connected to the conductive pattern; and a conductor made of a conductive material extending from the upper surface of the substrate through the first hole and the second hole to the lower surface of the substrate, wherein the conductor is formed onto the conductive pattern and is formed with an external connection terminal at the other end.
The conductive pattern may have a second hole formed at a location corresponding to the first hole, and the conductor may be formed by a conductive material extending through the first hole and the second hole.
In a still other aspect of the present invention, a surface mount type semiconductor package having a dielectric substrate with a first hole passing from an upper surface to a lower surface, a conductive pattern formed on the upper surface of the dielectric substrate, and a semiconductor chip mounted on the upper surface and electrically connected to the conductive pattern, comprises a conductor made of a conductive material extending from the upper surface through first hole to the lower surface and also onto the conductive pattern, the conductor being at one end electrically connected to the conductive pattern and at the other end formed with an external connection terminal.
The conductive pattern may have a first opening portion at a location corresponding to the through-hole, and the conductor may be formed by a conductive material extending through the through-hole and the first opening portion.
The first opening portion may be formed to have a circumference smaller than that of the through-hole.
An insulating film may be formed on the conductive pattern, a second opening portion, including a first opening portion, may be formed at a location corresponding to the first opening portion of the insulating film, and the conductor may be formed by a conductive material extending through the first and the second opening portions and the through-hole.
The upper surface of the conductive pattern may be exposed from the second opening portion, and the conductor may be formed by a conductive material extending from the upper surface of the conductive pattern through the first opening portion and the through-hole.